1. Field of the Invention
The present invention generally relates to computer chip manufacture and, more particularly, to providing copper wire connections without the copper poisoning inter-level dielectric oxide or bulk silicon.
2. Background Description
Forming wires and vias for connections can be done by a variety of methods. Typically, a substrate is covered with an insulator which is patterned for wires and vias. Metal is then deposited and any metal overlying the insulator is removed by chemical-mechanical polish (CMP). This process is known in the art as a damascene process.
The use of copper wires in computer chip manufacture is desirable because copper has a lower resistivity than aluminum and makes a better conductor. However, copper wiring requires special care in the production process. Copper requires an adhesion layer, thus adding steps to the production. In addition, copper diffuses easily through silicon and oxide, so a diffusion barrier between the copper wire and the silicon dioxide insulator is also required.
When forming vias to provide connection to copper wires, an argon sputter is performed as the first step prior to the metal deposition to fill the via. The purpose of the argon sputter is to remove the copper oxide from the copper wire below the via. Copper and copper oxide will be re-deposited on the via sidewalls during this argon sputter creating the possibility of copper diffusing into the oxide, poisoning it and degrading its electrical insulating capability.
Copper-insulator wiring structures can be formed by damascene or dual-damascene processes. One damascene level is fabricated by the deposition of planar dielectric stack which is then patterned and etched using standard lithographic and dry etch techniques to produce the wiring or via pattern. Metal deposition takes place next. Then, chemical-mechanical polishing is used to remove the field metal leaving the planarized wiring and via imbedded in the insulator. Subsequent levels are formed by repeating the above steps. In the damascene process all wiring is planar at each level. An adhesion layer and diffusion barrier is necessary in copper structures and is typically placed under the copper layers.